Emilio Andere's Recent LinkedIn Posts

deepseek bypassed NCCL for MoE communication. instead of routing every transfer through a CPU proxy, they do all-to-all dispatch in 77 microseconds. here's how DeepEP works under the hood: NCCL is built for symmetric collectives like allreduce, where every GPU sends and receives the same amount. MoE all-to-all is t…

the tech lead for TPUv3 software at Google published a 100+ page document on how to build a better AI chip than both TPUs and GPUs. you should go read the whole book, but here's a TLDR of the sections i found most interesting. the thesis is simple: the future is CPUs with systolic arrays. every AI chip is a systol…

NVIDIA and AMD instructions lives in one ISA. Qualcomm's hexagon NPU runs three separate instruction sets inside a single core. here's why: a hexagon core contains three physically separate compute units, each with its own instruction encoding, register file, and data types. the scalar processor is a 4-wide VLIW w…

Wrote the most comprehensive technical breakdown I could of why I believe AI inference hardware will become completely heterogeneous over the next decade. It covers AI inference hardware math from first principles, prefill/decode disaggregation, the Groq LP30 microarchitecture, and 12+ companies building decode-sp…

the tech lead for TPUv3 software at Google published a 100+ page document on how to build a better AI chip than both TPUs and GPUs. you should go read the whole book, but here's a TLDR of the sections i found most interesting. the thesis is simple: the future is CPUs with systolic arrays. every AI chip is a systol…

NVIDIA and AMD instructions lives in one ISA. Qualcomm's hexagon NPU runs three separate instruction sets inside a single core. here's why: a hexagon core contains three physically separate compute units, each with its own instruction encoding, register file, and data types. the scalar processor is a 4-wide VLIW w…